| Demonstration of FPGA-based A-IFoF/mmWave transceiver integration in mobile infrastructure for beyond 5G transport. | 0 | 0.34 | 2021 |
| Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution | 5 | 0.47 | 2019 |
| Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks. | 0 | 0.34 | 2019 |
| High Performance Accelerator for CNN Applications | 0 | 0.34 | 2019 |
| Scheduler Accelerator for TDMA Data Centers | 0 | 0.34 | 2018 |
| Nephele: Vertical Integration And Real-Time Demonstration Of An Optical Datacenter Network | 0 | 0.34 | 2018 |
| NEPHELE: An End-to-End Scalable and Dynamically Reconfigurable Optical Architecture for Application-Aware SDN Cloud Data Centers. | 1 | 0.37 | 2018 |
| Parallel Memory Accessing for FFT Architectures. | 0 | 0.34 | 2018 |
| Real Time Demonstration of an End-to-End Optical Datacenter Network with Dynamic Bandwidth Allocation | 0 | 0.34 | 2018 |
| Sdn Control Framework With Dynamic Resource Assignment For Slotted Optical Datacenter Networks | 0 | 0.34 | 2017 |
| Slotted TDMA and optically switched network for disaggregated datacenters | 0 | 0.34 | 2017 |
| A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs. | 0 | 0.34 | 2016 |
| Reduced Complexity Super-Resolution for Low-Bitrate Video Compression | 4 | 0.46 | 2016 |
| A Configurable Transmitter Architecture & Organization For Xg-Pon Olt/Onu/Ont Network Elements | 0 | 0.34 | 2015 |
| Towards real-time neuronal connectivity assessment: A scalable pipelined parallel generalized partial directed coherence engine | 0 | 0.34 | 2015 |
| Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms | 1 | 0.41 | 2014 |
| Using high-level synthesis to build memory and datapath optimized DSP accelerators | 0 | 0.34 | 2014 |
| XG-PON optical network unit downstream FEC design based on truncated Reed-Solomon code | 2 | 0.43 | 2014 |
| Single-image super-resolution using low complexity adaptive iterative back-projection | 1 | 0.35 | 2013 |
| Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs. | 5 | 0.42 | 2012 |
| Study of interpolation filters for motion estimation with application in H.264/AVC encoders. | 2 | 0.40 | 2011 |
| A Control-Theoretic Approach for Efficient Design of Filters in DAC and Digital Audio Amplifiers. | 1 | 0.36 | 2011 |
| A continuous-flow, Variable-Length FFT SDF architecture. | 2 | 0.41 | 2010 |
| An efficient dual-mode floating-point Multiply-Add Fused Unit. | 2 | 0.39 | 2010 |
| Programmable Motion Estimation architecture | 0 | 0.34 | 2009 |
| Efficient cascaded VLSI FFT architecture for OFDM systems. | 2 | 0.44 | 2009 |
| Evaluating the performance of a configurable, extensible VLIW processor in FFT execution. | 0 | 0.34 | 2009 |
| A real-time H.264/AVC VLSI encoder architecture | 8 | 0.64 | 2008 |
| A real-time motion estimation FPGA architecture | 11 | 0.66 | 2008 |
| Addressing technique for parallel memory accessing in radix-2 FFT processors | 4 | 0.46 | 2008 |
| A High Performance VLSI FFT Architecture. | 6 | 0.78 | 2006 |
| An Efficient H.264 VLSI Advanced Video Encoder | 4 | 0.48 | 2006 |
| A VLSI architecture for minimizing the transmission power in OFDM transceivers | 0 | 0.34 | 2003 |
