Name
Title | ||
|---|---|---|
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor |
Abstract | ||
|---|---|---|
A chip-multiprocessor is one of the promising architectures that can overcome the ILP limitation, high power consumption and high heating that current processors face. On a shared memory multiprocessor, a performance improvement relies on an efficient communication and synchronization method via shared variables. The TSVM cache combines communication and synchronization with the coherence maintenance on a chip-multiprocessor. That is, the communication and synchronization via shared variables are realized by one coherence transaction through a high- speed on chip inter-connection. The TSVM cache provides several instructions that each instruction has the individual coherence maintenance scheme. The combinations of these instructions can realize the producer-consumers synchronization, mutual exclusion and barrier synchronization with communication easily and systematically. This paper describes how those instructions construct three primitives and shows effect of these primitives using a clock cycle accurate simulator written in VHDL. The result shows that the TSVM cache can improve a performance of 9.8 times compared with a traditional cache memory, and improve a performance of 2 times compared with a conventional cache memory with synchronization mechanism. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISPAN.2005.27 | ISPAN |
Keywords | Field | DocType |
conventional cache memory,producer-consumers synchronization,synchronization mechanism,barrier synchronization,coherence maintenance,cache memory,synchronization method,efficient parallel processing,tsvm cache,shared variable,traditional cache memory,coherence maintenances,efficient communication,chip,hardware description languages,parallel processing,mutual exclusion,synchronisation | Cache invalidation,Cache pollution,Cache,Computer science,MESI protocol,Parallel computing,Cache algorithms,Cache coloring,Bus sniffing,Synchronization (computer science) | Conference |
ISBN | Citations | PageRank |
0-7695-2509-1 | 5 | 0.55 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Yamawaki | 1 | 17 | 9.36 |
| Masahiko Iwane | 2 | 13 | 3.79 |