Akira Yamawaki - Citegraph

Author Info

Name	Affiliation	Papers
AKIRA YAMAWAKI	Kyushu Institute of Technology, Kitakyushu, Japan	25
Collaborators	Citations	PageRank
22	17	9.36
Referers	Referees	References
26	249	81

Search Limit

100249

Publications (25 rows)

Collaborators (22 rows)

Referers (26 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Omnidirectional Background Scrolling in High-Level Synthesis Oriented Game Programing Library	0	0.34	2021
A performance evaluation of read/write burst transfer by high-level synthesizable software for the alpha blending processing	0	0.34	2020
Duplicating same argument of function to realize efficient hardware for high-level synthesis	1	0.43	2020
Proposal of an ultrasonic sensor array with flexible and scalable organization	0	0.34	2019
Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library	0	0.34	2019
A Describing Method Of An Image Processing Software In C For A High-Level Synthesis Considering A Function Chaining	0	0.34	2018
Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation	0	0.34	2018
Construction Of Parallel Random I/O Codes Using Coset Coding With Hamming Codes	0	0.34	2018
An Upper Bound On The Generalized Cayley Distance	0	0.34	2018
Unrestricted-Rate Parallel Random Input-Output Codes For Multilevel Flash Memory	0	0.34	2018
Construction of Unrestricted Rate Parallel Random Input Output Code.	0	0.34	2017
Worst-Case Performance Of Ilifc With Inversion Cells	0	0.34	2017
Battery Life Estimation of Sensor Node with Zero Standby Power Consumption	0	0.34	2016
A sensor node architecture with zero standby power on wireless sensor network	1	0.36	2015
Underwater optical image dehazing using guided trigonometric bilateral filtering	3	0.41	2013
A method using the same light sensor for detecting multiple events near a window in crimes involving intrusion into a home	0	0.34	2010
An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA	0	0.34	2010
An efficient hardware architecture from c program with memory access to hardware	0	0.34	2010
An intermediate hardware model with load/store unit for C to FPGA	0	0.34	2009
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware	1	0.38	2009
A Programmable Load/Store Unit on C-based Hardware Design for FPGA	0	0.34	2007
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip	2	0.60	2007
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor	5	0.55	2005
Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip	2	0.44	2002
Tagged communication and synchronization memory for multiprocessor-on-a-chip	2	0.45	2001