Name
Title | ||
|---|---|---|
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces |
Abstract | ||
|---|---|---|
We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As a result, the simulation is orders of magnitude faster than an instruction level one but the methodology is not valid with a dynamically scheduled superscalar microprocessor. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/EURMIC.1997.617340 | Budapest, Hungary |
Keywords | Field | DocType |
memory architecture,microcomputers,performance evaluation,storage management,virtual machines,PC microcomputers,commodity chips,desktop PC,dynamically scheduled superscalar microprocessor,memory hierarchy simulation,performance evaluation,synthetic bus traces | Registered memory,Interleaved memory,Memory hierarchy,Extended memory,Computer science,DOS memory management,Memory management,Conventional memory,Memory map,Operating system,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-6503 | 0-8186-8129-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pavlov, A. | 1 | 0 | 0.34 |
| Jean-Luc Béchennec | 2 | 56 | 11.21 |
| Daniel Etiemble | 3 | 300 | 42.43 |