Name
Abstract | ||
|---|---|---|
A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.1414 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
Phase Change RAMs, Verilog-A model, macromodel, Multi Level Cell, resistive memories | Multi-level cell,Computer science,Simulation,Spice,Phase change,Electronic engineering,Verilog-A | Journal |
Volume | Issue | ISSN |
6 | 19 | 1349-2543 |
Citations | PageRank | References |
4 | 0.74 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kwan-Hee Jo | 1 | 4 | 1.42 |
| Ji-Hye Bong | 2 | 8 | 2.88 |
| Kyeong-Sik Min | 3 | 18 | 5.39 |
| Sung-Mo Steve Kang | 4 | 1198 | 213.14 |