Paper Info
Title
RAM-based FPGA's: a test approach for the configurable logic
Abstract
This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.
Year
DOI
Venue
1998
10.1109/DATE.1998.655840
DATE
Keywords
Field
DocType
test approach,test configurations,fpga size,basic test configurations,ram-based fpgas,iterative array,c-testability property,one-dimensional iterative array,configurable logic,proposed test configurations,flexible device,controllability,high level synthesis,manufacturing,application specific integrated circuits,field programmable gate arrays,observability
Logic synthesis,Sequential logic,Computer science,Programmable Array Logic,Logic optimization,Parallel computing,Programmable logic array,Field-programmable gate array,Logic family,Built-in self-test
Conference
ISBN
Citations 
PageRank 
0-8186-8359-7
18
1.30
References 
Authors
10
4
Name
Order
Citations
PageRank
M. Renovell122418.93
J. M. Portal217620.95
J. Figueras322719.91
Y. Zorian449947.97