Name
Title | ||
|---|---|---|
Selective Scan Slice Repetition For Simultaneous Reduction Of Test Power Consumption And Test Data Volume |
Abstract | ||
|---|---|---|
In this paper, we present a selective scan slice encoding technique for power-aware test data compression. The proposed scheme dramatically reduces test data volume via scan slice repetition, and generates an adjacent-filled test pattern known as the favorable low-power pattern mapping method. Experiments were performed on the large ITC'99 benchmark circuits, and results show the effectiveness of the proposed method. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.1432 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
design-for-testability, low-power testing, scan testing, test data compression | Design for testing,Wafer,Computer science,Scan chain,Electronic engineering,Test data compression,Test data,Computer hardware,Test compression,Electronic circuit,Encoding (memory) | Journal |
Volume | Issue | ISSN |
6 | 20 | 1349-2543 |
Citations | PageRank | References |
5 | 0.45 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong-Joon Kim | 1 | 118 | 13.73 |
| Jaeseok Park | 2 | 19 | 6.05 |
| Sungho Kang | 3 | 436 | 78.44 |