Name
Abstract | ||
|---|---|---|
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network must be able to communicate between cells in di erent clock domains, and do so with minimal space, power, and latency overhead. In this paper, we describe an asynchronous NoC using an elastic-flow protocol, and methods of automatically generating a topology and router placement. We use the communication profile of the SoC design to drive the binary-tree topology creation and the physical placement of routers, and a force-directed approach to determine router locations. The nature of elastic-flow removes the need for large router bu ers, and thus we gain a significant power and space advantage compared to traditional NoCs. Additionally, our network is deadlock-free, and paths have bounded worst-case communication latencies. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1016/j.entcs.2008.02.003 | Electr. Notes Theor. Comput. Sci. |
Keywords | Field | DocType |
specific network-on-chip,router location,network-on-chip,elastic flow,large router bu ers,router placement,vlsi,elastic-flow protocol,gals,soc design,minimal space,binary-tree topology creation,communication profile,asynchronous noc,asynchronous,large number,intellectual property,network on chip,system on chip,binary tree | Asynchronous communication,Computer science,Latency (engineering),Network on a chip,Core router,Router,Interconnection,Very-large-scale integration,One-armed router,Embedded system | Journal |
Volume | Issue | ISSN |
200 | 1 | Electronic Notes in Theoretical Computer Science |
Citations | PageRank | References |
10 | 0.84 | 16 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Gebhardt | 1 | 10 | 0.84 |
| Kenneth S. Stevens | 2 | 185 | 25.65 |