Name
Abstract | ||
|---|---|---|
Two-pattern tests target the detection of most commonfailure mechanisms in cmos vlsi circuits, which aremodeled as stuck-open or delay faults. In this paper theAccumulator-Based Two-pattern generation (ABT) algorithm ispresented, that generates an exhaustive n-bit two-pattern testwithin exactly 2^n × (2^n − 1) + 1 clock cycles, i.e. within thetheoretically minimum time. The ABT algorithm is implementedin hardware utilizing an accumulator whose inputs are driven byeither a binary counter (counter-based implementation) or a LinearFeedback Shift Register (LFSR-based implementation). With thecounter-based implementation different modules, having differentnumber of inputs, can be efficiently tested using the samegenerator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (thattypically drive the accumulator inputs into dapatapath cores) can beeasily modified to LFSRS with small increase in the hardwareoverhead. The great advantage of the presented scheme is that it canbe implemented by augmening existing datapath components, rather thanbuilding a new pattern generation structure. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1023/A:1008340925177 | J. Electronic Testing |
Keywords | Field | DocType |
built-in self test,delay fault testing,stuck-open fault testing,two-pattern testing | Datapath,Pattern generation,Computer science,Electronic engineering,Real-time computing,Electronic circuit,Minimum time,Cmos vlsi circuits,Accumulator (structured product),Binary number,Built-in self-test | Journal |
Volume | Issue | ISSN |
15 | 3 | 1573-0727 |
Citations | PageRank | References |
7 | 0.47 | 13 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| I. Voyiatzis | 1 | 39 | 9.33 |
| A. Paschalis | 2 | 358 | 31.08 |
| D. Nikolos | 3 | 291 | 31.38 |
| Constantin Halatsis | 4 | 33 | 3.15 |