Name
Abstract | ||
|---|---|---|
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, their effectiveness are often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DATE.2005.81 | Clinical Orthopaedics and Related Research |
Keywords | Field | DocType |
improve circuit performance,execution time,original specification,scheduling,circuit latency,time-constrained scheduling problem,scheduling algorithms,optimized specification,circuit area,behavioural specifications,specification operation,circuit optimisation,behavioural transformation,optimization,data-dependent operation fragment,behavioural specification,circuit performance,high-level synthesis,faster operation,high level synthesis,formal specification,crossbar,scheduling problem,hardware architecture,bus,scheduling algorithm,routing | Chaining,Job shop scheduling,Scheduling (computing),Computer science,Parallel computing,High-level synthesis,Formal specification,Real-time computing,Cycles per instruction,Electronic circuit,Crossbar switch | Conference |
ISSN | ISBN | Citations |
1530-1591 | 0-7695-2288-2 | 5 |
PageRank | References | Authors |
0.48 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rafael Ruiz-Sautua | 1 | 32 | 5.28 |
| M. C. Molina | 2 | 70 | 7.44 |
| J. M. Mendias | 3 | 121 | 9.25 |
| Román Hermida | 4 | 89 | 15.34 |