Name
Abstract | ||
|---|---|---|
Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary switching functions. The logic circuits operate in voltage mode where different ranges of voltages encode the logic levels. Voltage mode circuitry is used to minimize overall power dissipation characteristics. Analysis of the resulting multiplication circuits indicates that power dissipation characteristics are advantageous when compared to equivalent word-sized binary voltage mode configurations with no decrease in performance. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISMVL.2010.32 | ISMVL |
Keywords | Field | DocType |
field effect transistors,field effect transistor,switches,power dissipation,mathematical model,multiplexing,logic gates,logic design,voltage,fixed point arithmetic,logic circuits,transistors,arithmetic,fixed point | Diode–transistor logic,Logic gate,Pull-up resistor,Pass transistor logic,Computer science,Emitter-coupled logic,Electronic engineering,Logic level,Logic family,Integrated injection logic,Electrical engineering | Conference |
ISSN | Citations | PageRank |
0195-623X | 1 | 0.42 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satyendra R. Datla | 1 | 8 | 0.95 |
| Mitchell A. Thornton | 2 | 280 | 40.94 |