| Rapid Ransomware Detection through Side Channel Exploitation | 0 | 0.34 | 2021 |
| A Quantum Photonic TRNG based on Quaternary Logic | 0 | 0.34 | 2020 |
| Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms | 0 | 0.34 | 2020 |
| Quantum Logic Synthesis with Formal Verification | 0 | 0.34 | 2019 |
| Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams | 0 | 0.34 | 2019 |
| Entanglement in Higher-Radix Quantum Systems. | 0 | 0.34 | 2019 |
| Multiple-Valued Random Digit Extraction | 0 | 0.34 | 2018 |
| Higher-Radix Chrestenson Gates for Photonic Quantum Computation. | 0 | 0.34 | 2018 |
| A Radix-4 Chrestenson Gate for Optical Quantum Computation | 0 | 0.34 | 2018 |
| Automated Markov-chain based analysis for large state spaces. | 0 | 0.34 | 2017 |
| Simulation of switching circuits using transfer functions | 0 | 0.34 | 2017 |
| QMDDs: Efficient Quantum Function Representation and Manipulation | 16 | 0.86 | 2016 |
| A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System. | 1 | 0.36 | 2016 |
| Demographic Group Prediction Based on Smart Device User Recognition Gestures | 0 | 0.34 | 2016 |
| Reliability Block Diagram Extensions For Non-Parametric Probabilistic Analysis | 0 | 0.34 | 2016 |
| Demographic Group Classification of Smart Device Users | 1 | 0.37 | 2015 |
| Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables. | 1 | 0.36 | 2015 |
| Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams. | 1 | 0.37 | 2015 |
| Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems | 0 | 0.34 | 2015 |
| Setting the stage for CE2016: A revised body of knowledge | 2 | 0.65 | 2014 |
| Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach. | 0 | 0.34 | 2014 |
| System Probability Distribution Modeling Using MDDs | 2 | 0.39 | 2014 |
| Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams | 1 | 0.35 | 2014 |
| On Optimizations Of Edge-Valued Mdds For Fast Analysis Of Multi-State Systems | 2 | 0.39 | 2014 |
| Spectral Response of Ternary Logic Netlists | 1 | 0.44 | 2013 |
| Computer engineering curriculum guidelines | 0 | 0.34 | 2013 |
| A Transfer Function Model for Ternary Switching Logic Circuits | 2 | 0.49 | 2013 |
| Ternary Logic Network Justification Using Transfer Matrices | 1 | 0.44 | 2013 |
| Embedded and real-time systems classes in traditional and distance education format | 0 | 0.34 | 2013 |
| Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation | 0 | 0.34 | 2012 |
| Uncle - An RTL Approach to Asynchronous Design | 18 | 0.90 | 2012 |
| Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams | 6 | 0.53 | 2012 |
| Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits | 0 | 0.34 | 2012 |
| Reversible Logic Synthesis Based on Decision Diagram Variable Ordering. | 0 | 0.34 | 2012 |
| Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities | 17 | 0.99 | 2011 |
| On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams | 2 | 0.43 | 2011 |
| To PE or not to PE: the Sequel | 1 | 0.34 | 2010 |
| Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits | 1 | 0.42 | 2010 |
| Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog© | 2 | 0.39 | 2009 |
| A Low Power High Performance Radix-4 Approximate Squaring Circuit | 7 | 0.54 | 2009 |
| On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering | 2 | 0.37 | 2009 |
| Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics | 1 | 0.35 | 2009 |
| A Discrete Logarithm Number System for Integer Arithmetic Modulo 2^{k}: Algorithms and Lookup Structures | 2 | 0.36 | 2009 |
| Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits | 22 | 1.13 | 2008 |
| Quantum Logic Implementation of Unary Arithmetic Operations | 4 | 0.51 | 2008 |
| On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams | 2 | 0.38 | 2008 |
| Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility | 3 | 0.49 | 2008 |
| Components And Analysis Of Disaster Tolerant Computing | 1 | 0.35 | 2007 |
| Advances in Quantum Computing Fault Tolerance and Testing | 2 | 0.49 | 2007 |
| Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL | 0 | 0.34 | 2007 |
