Name
Abstract | ||
|---|---|---|
Vector reordering is an essential task in testing VLSI systems because it affects this process from two perspectives: power consumption and correlation among data. The former feature is crucial and if not properly controlled during testing, may result in permanent failure of the device-under-test (DUT). The atter feature is a so important because correlation is captured by coding schemes to efficiently compress test data and ease memory requirements of Automatic-Test-Equipment (ATE),while reducing the volume of data and lowering the test application time. Reordering however is NP-complete. This paper presents an evaluation of different heuristic techniques for vector reordering using ISCAS85 and ISCAS89 benchmark circuits in terms of time and quality. For this application, it is shown that the best heuristic technique is not the famous Christofides or Lin-Kernighan, but the Multi-Fragment technique. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/988952.988976 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
former feature,test vector,multi-fragment technique,test application time,different heuristic technique,iscas89 benchmark circuit,heuristic technique,vlsi system,atter feature,vector reordering,compress test data,device under test,automatic test equipment,compression,test data,soc | Test vector,Heuristic,Computer science,Algorithm,Electronic engineering,Real-time computing,Coding (social sciences),Test data,Test compression,Electronic circuit,Fold (higher-order function),Power consumption | Conference |
ISBN | Citations | PageRank |
1-58113-853-9 | 3 | 0.44 |
References | Authors | |
12 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. Hashempour | 1 | 127 | 15.11 |
| F. Lombardi | 2 | 122 | 15.25 |