Name
Title | ||
|---|---|---|
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality |
Abstract | ||
|---|---|---|
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DATE.2005.199 | Clinical Orthopaedics and Related Research |
Keywords | Field | DocType |
delay test quality,high frequency clock domain,test quality,expensive test equipment,on-chip high-speed clock generation,test vector count,logic design,on-chip test clock generation,on-chip clock generation,paper addresses delay test,implementation details,atpg result,soc device,soc,chip,fault coverage,production,automatic test pattern generation,atpg,system on chip,system on a chip,design for testability,fpga,high frequency | Logic synthesis,Design for testing,Test vector,Automatic test pattern generation,Computer science,Field-programmable gate array,Real-time computing,Digital clock manager,Test compression,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005) | 0-7695-2288-2 | 21 |
PageRank | References | Authors |
1.10 | 17 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Beck | 1 | 34 | 2.19 |
| Olivier Barondeau | 2 | 28 | 1.74 |
| Martin Kaibel | 3 | 24 | 1.60 |
| Frank Poehl | 4 | 34 | 2.19 |
| Xijiang Lin | 5 | 687 | 42.03 |
| Ron Press | 6 | 113 | 9.12 |