Name
Abstract | ||
|---|---|---|
As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays. In a 3D IC stack, all but the bottom tier are thinned down to enable through-silicon vias (TSV). However, the thinning of the substrate increases the lateral thermal resistance resulting in higher intra-layer temperature gradients potentially leading to performance degradation and even functional errors. In this work, we study the effect of thinning the substrate on temperature profile of various tiers in 3D ICs. Our simulation results show that the intra-layer temperature gradient can be as high as 57°C. Often, the conventional static solutions lead to highly inefficient design. To this end, we present a system-level situation-aware integrated scheme that performs opportunistic thread migration and dynamic voltage and frequency scaling (DVFS) to effectively manage thermal violations while increasing the system throughput relative to stand-alone schemes. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISQED.2013.6523595 | ISQED |
Keywords | Field | DocType |
stacked 3d integrated circuit,substrate the,tsv,integrated circuit interconnections,thermal resistance,power dissipation,dynamic voltage and frequency scaling (dvfs),intralayer temperature gradient,three-dimensional integrated circuits,opportunistic thread migration,3d ic stack,system-level situation-aware integrated scheme,dynamic voltage scaling,interconnect delay,integration density,thermal management (packaging),cmos technology,frequency scaling,dynamic thermal management,substrate thinning,lateral thermal resistance,thermal violation management,dvfs,thread migration,thinned 3d ic,3d ic,spatial temperature gradient management,heterogeneous stacking,through-silicon vias,spatial gradient,temperature profile,registers,switches,integrated circuits,thermal analysis | Computer science,Dissipation,Electronic engineering,CMOS,Frequency scaling,Three-dimensional integrated circuit,Temperature gradient,Interconnection,Integrated circuit,Electrical engineering,Thermal resistance | Conference |
ISSN | ISBN | Citations |
1948-3287 | 978-1-4673-4951-2 | 2 |
PageRank | References | Authors |
0.39 | 22 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arunachalam Annamalai | 1 | 84 | 5.67 |
| Raghavan Kumar | 2 | 73 | 12.56 |
| Arunkumar Vijayakumar | 3 | 44 | 4.65 |
| Sandip Kundu | 4 | 1103 | 137.18 |