Name
Abstract | ||
|---|---|---|
The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the number of load instructions that reach the cache hierarchy. We introduce the notion of zero loads to approach the latter. This paper explores the potential of tracking locations that contain the value 'zero'. Loads directed to such locations -- termed Zero Loads -- can be cancelled before they are issued in the cache hierarchy. We find that as many as 21% of the loads are Zero Loads and about one third of them are critical, i.e., ends up on the critical memory path for out-of-order cores. Motivated by this observation, we explore two innovative structures to capture Zero Loads by essentially book-keeping earlier visited blocks/locations that return 'zero'. These schemes are shown to be capable of improving performance and power/energy efficiency considerably. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1509084.1509087 | Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture |
Keywords | DocType | Citations |
load request,cache management,load criticality,cache,zero loads,power loss,value locality,cache-hierarchy efficiency,prediction,cache hierarchy call,dram speed,critical memory path,zero value,zero load,cache hierarchy,energy efficiency,out of order,energy efficient | Conference | 2 |
PageRank | References | Authors |
0.40 | 27 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mafijul Md. Islam | 1 | 42 | 6.13 |
| Per Stenström | 2 | 3048 | 234.09 |