| Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints | 0 | 0.34 | 2022 |
| GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases | 0 | 0.34 | 2022 |
| Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications | 0 | 0.34 | 2022 |
| DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors | 0 | 0.34 | 2020 |
| A GPU Register File using Static Data Compression | 0 | 0.34 | 2020 |
| Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints | 0 | 0.34 | 2020 |
| Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems | 1 | 0.35 | 2020 |
| Global Dead-Block Management for Task-Parallel Programs. | 0 | 0.34 | 2018 |
| SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. | 2 | 0.38 | 2017 |
| Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. | 0 | 0.34 | 2017 |
| A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs. | 1 | 0.35 | 2017 |
| Timing-anomaly free dynamic scheduling of task-based parallel applications | 1 | 0.35 | 2017 |
| Euroserver: Share-Anything Scale-Out Micro-Server Design | 5 | 0.87 | 2016 |
| 2015 Maurice Wilkes Award Given to Christos Kozyrakis. | 0 | 0.34 | 2016 |
| PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor | 6 | 0.41 | 2016 |
| Enhancing Garbage Collection Synchronization using Explicit Bit Barriers | 0 | 0.34 | 2015 |
| HyComp: a hybrid cache compression method for selection of data-type-specific compression methods | 9 | 0.44 | 2015 |
| Overhead-aware temporal partitioning on multicore processors | 3 | 0.41 | 2014 |
| SC2: a statistical compression cache scheme | 31 | 0.78 | 2014 |
| Removal of Conflicts in Hardware Transactional Memory Systems | 1 | 0.35 | 2014 |
| Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing. | 0 | 0.34 | 2014 |
| Effective resource management towards efficient computing | 0 | 0.34 | 2014 |
| Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell | 4 | 0.41 | 2014 |
| Moving from petaflops to petadata | 10 | 0.81 | 2013 |
| Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory | 4 | 0.39 | 2013 |
| Transactional prefetching: narrowing the window of contention in hardware transactional memory | 1 | 0.35 | 2012 |
| ZEBRA: a data-centric, hybrid-policy hardware transactional memory design | 12 | 0.55 | 2011 |
| Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory | 8 | 0.43 | 2011 |
| Classification and Elimination of Conflicts in Hardware Transactional Memory Systems | 3 | 0.37 | 2011 |
| A unified approach to eliminate memory accesses early | 2 | 0.37 | 2011 |
| LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems | 2 | 0.37 | 2010 |
| Transactions on High-Performance Embedded Architectures and Compilers I | 46 | 4.32 | 2009 |
| Schemes for avoiding starvation in transactional memory systems | 1 | 0.35 | 2009 |
| Using Hoarding to Increase Availability in Shared File Systems | 0 | 0.34 | 2009 |
| A Flexible Code Compression Scheme Using Partitioned Look-Up Tables | 6 | 0.51 | 2009 |
| Zero loads: canceling load requests by tracking zero values | 2 | 0.40 | 2008 |
| Memory-Link Compression Schemes: A Value Locality Perspective | 28 | 1.25 | 2008 |
| Early detection and bypassing of trivial operations to improve energy efficiency of processors | 0 | 0.34 | 2008 |
| High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings | 25 | 1.90 | 2008 |
| Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression | 0 | 0.34 | 2008 |
| Leveraging Data Promotion for Low Power D-NUCA Caches | 14 | 0.65 | 2008 |
| Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007 | 30 | 2.65 | 2007 |
| High-Performance Embedded Architecture and Compilation Roadmap | 26 | 1.64 | 2007 |
| Implicit transactional memory in kilo-instruction multiprocessors | 3 | 0.44 | 2007 |
| IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? | 1 | 0.35 | 2007 |
| Loop-level Speculative Parallelism in Embedded Applications | 2 | 0.42 | 2007 |
| Microprocessors in the Era of Terascale Integration | 25 | 1.19 | 2007 |
| High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings | 19 | 1.09 | 2007 |
| An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches | 8 | 0.50 | 2007 |
| Introduction to Part 1 | 0 | 0.34 | 2007 |
