Title
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
Abstract
This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual VSS control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.
Year
DOI
Venue
2014
10.1109/TCSII.2013.2296137
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
tsmc cmos technology,cmos integrated circuits,half-select,read stack,multiport sram,power consumption,column-based virtual vss control,two-port (tp),register file applications,nanoscale cmos technology,shared write bit-lines,size 40 nm,sram chips,read path,low-power electronics,static noise margin,cross-point write word-lines,leakage,low-power multiport sram,multiport networks,write/read current consumption,shared write row-access transistors,low power electronics,transistors,registers
Transistor count,Leakage (electronics),Computer science,Register file,Electronic engineering,Static random-access memory,Chip,CMOS,Computer hardware,Transistor,Low-power electronics
Journal
Volume
Issue
ISSN
61
3
1549-7747
Citations 
PageRank 
References 
2
0.40
5
Authors
4
Name
Order
Citations
PageRank
Dao-Ping Wang151.32
Hon-Jarn Lin282.07
Ching-Te Chuang346576.52
Wei Hwang425444.40