Name
Abstract | ||
|---|---|---|
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multi-bank local memory, and a row of PEs share memory access. In order for each row of the PEs to access any memory bank, there is a hardware arbiter between the memory requests generated by the PEs and the banks of the local memory. However, a fundamental restriction remains that a bank cannot be accessed by two different PEs at the same time. We propose to meet this challenge by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts. Our experimental results on kernels from multimedia benchmarks demonstrate that our local memory-aware compilation approach can generate mappings that are up to 40% better in performance (17.3% on average) compared to a memory-unaware scheduler. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1755888.1755892 | Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems |
Keywords | Field | DocType |
power efficiency,shared memory | Electrical efficiency,Memory bank,Arbiter,Interleaved memory,Data mapping,Computer science,Scheduling (computing),Parallel computing,Input/output,Real-time computing,Energy consumption | Conference |
Volume | Issue | ISSN |
45 | 4 | 0362-1340 |
Citations | PageRank | References |
12 | 0.60 | 16 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongjoo Kim | 1 | 125 | 10.86 |
| Jongeun Lee | 2 | 429 | 33.71 |
| Aviral Shrivastava | 3 | 812 | 68.67 |
| Yunheung Paek | 4 | 935 | 76.05 |