| Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor | 0 | 0.34 | 2020 |
| Learning To Predict Ir Drop With Effective Training For Reram-Based Neural Network Hardware | 0 | 0.34 | 2020 |
| Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing | 3 | 0.40 | 2019 |
| Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs | 4 | 0.48 | 2019 |
| Efficient FPGA implementation of local binary convolutional neural network. | 0 | 0.34 | 2019 |
| An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. | 1 | 0.36 | 2018 |
| Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. | 2 | 0.37 | 2018 |
| FPGA implementation of convolutional neural network based on stochastic computing | 1 | 0.35 | 2017 |
| Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs. | 3 | 0.41 | 2017 |
| A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks. | 6 | 0.53 | 2017 |
| Design space exploration of FPGA accelerators for convolutional neural networks. | 4 | 0.45 | 2017 |
| Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. | 29 | 1.45 | 2016 |
| Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures. | 0 | 0.34 | 2016 |
| Efficient Fpga Acceleration Of Convolutional Neural Networks Using Logical-3d Compute Array | 18 | 1.00 | 2016 |
| An energy-efficient random number generator for stochastic circuits | 10 | 0.67 | 2016 |
| Optimizing stream program performance on CGRA-based systems | 3 | 0.41 | 2015 |
| Improving performance of loops on DIAM-based VLIW architectures | 0 | 0.34 | 2014 |
| Design and optimization for embedded and real-time computing systems and applications. | 0 | 0.34 | 2014 |
| Configurable range memory for effective data reuse on programmable accelerators | 0 | 0.34 | 2014 |
| Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures | 0 | 0.34 | 2014 |
| Architecture customization of on-chip reconfigurable accelerators | 1 | 0.35 | 2013 |
| Evaluator-executor transformation for efficient pipelining of loops with conditionals. | 2 | 0.37 | 2013 |
| A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. | 5 | 0.71 | 2013 |
| Software-based register file vulnerability reduction for embedded processors | 1 | 0.35 | 2013 |
| Compiling control-intensive loops for CGRAs with state-based full predication | 12 | 0.61 | 2013 |
| Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs | 7 | 0.50 | 2013 |
| PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems | 0 | 0.34 | 2012 |
| Improving performance of nested loops on reconfigurable array processors | 22 | 1.06 | 2012 |
| Return Data Interleaving for Multi-Channel Embedded CMPs Systems | 2 | 0.37 | 2012 |
| Exploiting both pipelining and data parallelism with SIMD reconfigurable architecture | 2 | 0.37 | 2012 |
| A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. | 9 | 0.71 | 2012 |
| I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics. | 0 | 0.34 | 2011 |
| High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures | 13 | 0.65 | 2011 |
| CRM: Configurable Range Memory for Fast Reconfigurable Computing | 2 | 0.47 | 2011 |
| Memory access optimization in compilation for coarse-grained reconfigurable architectures | 6 | 0.49 | 2011 |
| Static Analysis of Register File Vulnerability | 14 | 0.77 | 2011 |
| Fast graph-based instruction selection for multi-output instructions | 1 | 0.37 | 2011 |
| Memory-Aware application mapping on coarse-grained reconfigurable arrays | 9 | 0.61 | 2010 |
| Binary acceleration using coarse-grained reconfigurable architecture | 8 | 0.62 | 2010 |
| Operation and data mapping for CGRAs with multi-bank memory | 12 | 0.60 | 2010 |
| A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files | 12 | 0.77 | 2010 |
| A software solution for dynamic stack management on scratch pad memory | 17 | 0.67 | 2009 |
| Static analysis to mitigate soft errors in register files | 9 | 0.69 | 2009 |
| A software-only solution to use scratch pads for stack data | 8 | 0.54 | 2009 |
| FSAF: file system aware flash translation layer for NAND flash memories | 5 | 0.76 | 2009 |
| Compiler-managed register file protection for energy-efficient soft error reduction | 3 | 0.43 | 2009 |
| SDRM: simultaneous determination of regions and function-to-region mapping for scratchpad memories | 25 | 0.84 | 2008 |
| Static analysis of processor stall cycle aggregation | 2 | 0.40 | 2008 |
| Evaluating Memory Architectures For Media Applications On Coarse-Grained Reconfigurable Architectures | 5 | 0.52 | 2008 |
| Hanmadang: entertainment systems for massive face-to-face interaction | 0 | 0.34 | 2008 |
