Name
Abstract | ||
|---|---|---|
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A Open image in new window pixel proof-of-concept chip was fabricated in a 0.35 Open image in new window m standard CMOS process, with a pixel size of 35 Open image in new window m Open image in new window 35 Open image in new window m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1155/2008/961315 | Eurasip Journal on Embedded Systems |
Keywords | DocType | Volume |
programmable mask-based image processing,vision chip,low-level image processing,parallel architecture,four-quadrant multiplier architecture,high-speed focal plane image,pixel proof-of-concept chip,simd programmable vision chip,raw image,pixel size,vlsi image acquisition,low-level image processing system | Journal | 2008, |
Issue | ISSN | Citations |
1 | 1687-3963 | 1 |
PageRank | References | Authors |
0.38 | 17 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dominique Ginhac | 1 | 105 | 17.27 |
| Jérôme Dubois | 2 | 4 | 1.56 |
| Michel Paindavoine | 3 | 115 | 21.70 |
| B. Heyrman | 4 | 49 | 5.88 |