Paper Info
Title
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
Abstract
Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the previous results of AVPG.
Year
DOI
Venue
2002
10.1109/TCAD.2002.802266
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
embedded cores,MCNC benchmarks,verification complexity,integrated circuit testing,design verification,automorphic approach,mcnc benchmarks,run time,core-based design,soc design verification,automatic test pattern generation,high complexity,verification pattern generation,mixed analogue-digital integrated circuits,core-based design verification,ISCAS-85 benchmarks,characteristic vector,pattern set size,corresponding verification pattern generation,design for testability,embedded systems,automorphic technique,interconnection verification,interconnection testing,pof model,SoC design verification,superset of all automorphism,port-order fault model,automatic verification pattern generation,IEEE P1500 standard for embedded core test
Journal
21
Issue
ISSN
Citations 
10
0278-0070
3
PageRank 
References 
Authors
0.44
8
3
Name
Order
Citations
PageRank
Wang Chun-Yao125136.08
Shing-Wu Tung2336.60
Jing-Yang Jou368188.55