Shing-Wu Tung - Citegraph

Author Info

Name	Affiliation	Papers
SHING-WU TUNG	Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan	15
Collaborators	Citations	PageRank
18	33	6.60
Referers	Referees	References
42	100	64

Publications (15 rows)

Collaborators (18 rows)

Referers (42 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform	0	0.34	2013
A 42.5µW/MHz ultra-low power 32-bit microcontroller — SPARK	0	0.34	2013
A power management technology for mobile embedded system	0	0.34	2012
Low power design and dynamic power management system for VLIW DSP subsystem	1	0.36	2011
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology	2	0.45	2011
SoC design integration by using automatic interconnection rectification	0	0.34	2003
An automatic interconnection rectification technique for SoC design integration	0	0.34	2003
Automatic interconnection rectification for SoC design verification based on the port order fault model	4	0.52	2003
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model	3	0.44	2002
On Automatic-Verification Pattern Generation For Soc With Port-Order Fault Model	4	0.47	2002
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model	0	0.34	2001
An AVPG for SOC design verification with port order fault model	6	0.59	2001
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model	3	0.46	2001
A Logical Fault Model for Library Coherence Checking	1	0.37	1998
Verification pattern generation for core-based design using port order fault model	9	0.92	1998

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