Name
Title | ||
|---|---|---|
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification |
Abstract | ||
|---|---|---|
A register-transfer level (RTL) circuit meeting a design specification may contain some functionally unused paths.If functionally unused paths can be easily identified at RTL,the information can be utilized to eliminate the corresponding gate-level paths from the target of testing.Testing such gate-level paths is considered to be futile. In this paper, we present a method for identifying such functionally unused paths, called RTL don't care paths, using RTL information, and a method of synthesis for transforming the identified paths into untestable paths which will never do a mischief.As a result, our approaches contribute to identification of many untestable paths and reduction of over-testing. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/VTS.2009.27 | VTS |
Keywords | Field | DocType |
register-transfer level,gate-level path,care path identification,synthesis method,design specification,corresponding gate-level path,rtl information,untestable path,functionally unused path,central processing unit,register transfer level,logic gates,logic design,very large scale integration,logic circuits,data mining,registers,probability density function,combinational circuits,digital circuits,information science | Logic synthesis,Logic gate,Computer science,Logic testing,Real-time computing,Electronic engineering,Design specification,Probability density function | Conference |
ISSN | ISBN | Citations |
1093-0167 | 978-0-7695-3598-2 | 3 |
PageRank | References | Authors |
0.43 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuki Yoshikawa | 1 | 28 | 4.51 |
| Satoshi Ohtake | 2 | 135 | 21.62 |
| Tomoo Inoue | 3 | 352 | 47.23 |
| Hideo Fujiwara | 4 | 184 | 20.31 |