| Temperature Monitoring in Shinkansen Signal and Communication House | 0 | 0.34 | 2020 |
| A Koji Temperature Monitoring System | 1 | 0.43 | 2019 |
| Factory Environment Monitoring: A Japanese Tea Manufacturer'S Case | 0 | 0.34 | 2019 |
| A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures | 0 | 0.34 | 2019 |
| Monitoring Sake Brewing Processes with Compact Wireless Sensors | 1 | 0.43 | 2019 |
| A Method of Hardware-Trojan Detection Using Design Verification Techniques. | 0 | 0.34 | 2018 |
| An approach to LFSR-based X-masking for built-in self-test | 0 | 0.34 | 2017 |
| A method of LFSR seed generation for hierarchical BIST | 0 | 0.34 | 2015 |
| A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults | 7 | 0.54 | 2015 |
| A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model | 0 | 0.34 | 2015 |
| A Method of Diagnostic Test Generation for Transition Faults | 0 | 0.34 | 2015 |
| A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG | 1 | 0.45 | 2013 |
| Delay Testing: Improving Test Quality and Avoiding Over-testing. | 0 | 0.34 | 2011 |
| F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG | 0 | 0.34 | 2011 |
| F-Scan: A Dft Method For Functional Scan At Rtl | 1 | 0.41 | 2011 |
| Enabling False Path Identification from RTL for Reducing Design and Test Futileness | 1 | 0.38 | 2010 |
| Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits | 0 | 0.34 | 2010 |
| A synthesis method to propagate false path information from RTL to gate level | 0 | 0.34 | 2010 |
| A Method Of Path Mapping From Rtl To Gate Level And Its Application To False Path Identification | 0 | 0.34 | 2010 |
| Constrained Atpg For Functional Rtl Circuits Using F-Scan | 2 | 0.37 | 2010 |
| A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification | 3 | 0.43 | 2009 |
| Fast false path identification based on functional unsensitizability using RTL information | 6 | 0.50 | 2009 |
| Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors | 0 | 0.34 | 2008 |
| Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths | 0 | 0.34 | 2008 |
| Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability | 0 | 0.34 | 2007 |
| Efficient path delay test generation based on stuck-at test generation using checker circuitry | 0 | 0.34 | 2007 |
| Low-Cost Hardening of Image Processing Applications Against Soft Errors | 16 | 0.97 | 2006 |
| Broadside Transition Test Generation For Partial Scan Circuits Through Stuck-At Test Generation | 0 | 0.34 | 2006 |
| Design for Testability Based on Single-Port-Change Delay Testing for Data Paths | 5 | 0.41 | 2005 |
| Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation | 3 | 0.41 | 2005 |
| A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency | 3 | 0.40 | 2005 |
| New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency | 0 | 0.34 | 2004 |
| A Design Methodology to Realize Delay Testable Controllers Using State Transition Information | 1 | 0.36 | 2004 |
| A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms | 3 | 0.41 | 2003 |
| Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models | 1 | 0.36 | 2003 |
| Design for two-pattern testability of controller-data path circuits | 3 | 0.38 | 2002 |
| A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits | 4 | 0.44 | 2002 |
| A nonscan DFT method for controllers to provide complete fault efficiency | 0 | 0.34 | 2002 |
| Design for Hierarchical Two-Pattern Testability of Data Paths | 10 | 0.64 | 2001 |
| Testable design of sequential circuits with improved fault efficiency | 1 | 0.35 | 2001 |
| A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability | 11 | 0.86 | 2001 |
| A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency | 10 | 0.98 | 2000 |
| A non-scan DFT method at register-transfer level to achieve complete fault efficiency | 17 | 1.17 | 2000 |
| A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description | 0 | 0.34 | 1999 |
| New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency | 6 | 0.56 | 1999 |
| A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency | 11 | 0.86 | 1998 |
| Sequential test generation based on circuit pseudo-transformation | 2 | 0.41 | 1997 |
| A sequential circuit structure with combinational test generation complexity and its application | 5 | 0.62 | 1997 |
