Name
Abstract | ||
|---|---|---|
Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/FPL.2012.6339257 | FPL |
Keywords | Field | DocType |
optimisation,virtex-6 fpga,maxeler max3424a system,gpu,stencil computation,reverse time migration,rtm,field-programmable accelerators,graphics processing units,cpu reference designs,field programmable gate arrays,run-time reconfiguration | Central processing unit,Reconfigurability,Scheduling (computing),Computer science,Parallel computing,Stencil code,Field-programmable gate array,Real-time computing,Exploit,Throughput,Control reconfiguration | Conference |
ISBN | Citations | PageRank |
978-1-4673-2255-3 | 16 | 0.85 |
References | Authors | |
14 | 5 | |