| Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. | 0 | 0.34 | 2018 |
| A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation. | 0 | 0.34 | 2018 |
| Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. | 11 | 0.60 | 2017 |
| IC security evaluation against fault injection attack based on FPGA emulation | 0 | 0.34 | 2016 |
| Cost Effective Partial Scan for Hardware Emulation | 0 | 0.34 | 2016 |
| Knowledge-Based Neural Network Model for FPGA Logical Architecture Development | 0 | 0.34 | 2016 |
| IP Protection of Mesh NoCs Using Square Spiral Routing | 1 | 0.36 | 2016 |
| Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems. | 1 | 0.40 | 2016 |
| A survey of hardware Trojan threat and defense. | 13 | 0.71 | 2016 |
| A Survey of Hardware Trojan Detection, Diagnosis and Prevention | 2 | 0.38 | 2015 |
| Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness | 0 | 0.34 | 2015 |
| A hierarchical IP protection approach for hard IP cores | 0 | 0.34 | 2015 |
| Pipelined NoC router architecture design with buffer configuration exploration on FPGA | 2 | 0.38 | 2015 |
| Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems | 3 | 0.42 | 2015 |
| Hardware Trojan detection acceleration based on word-level statistical properties management | 3 | 0.38 | 2014 |
| Automating Elimination of Idle Functions by Run-Time Reconfiguration | 9 | 0.79 | 2013 |
| Heterogeneous systems for energy efficient scientific computing | 11 | 0.58 | 2012 |
| Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms | 1 | 0.34 | 2012 |
| Exploiting run-time reconfiguration in stencil computation | 16 | 0.85 | 2012 |
| Optimizing Hardware Design by Composing Utility-Directed Transformations | 1 | 0.39 | 2012 |
| Objective-driven workload allocation in heterogeneous computing systems | 1 | 0.39 | 2011 |
| Power adaptive computing system design in energy harvesting environment | 2 | 0.37 | 2011 |
| Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation | 1 | 0.39 | 2011 |
| Combining optimizations in automated low power design | 16 | 0.99 | 2010 |
| Convex models for accelerating applications on FPGA-based clusters | 2 | 0.45 | 2010 |
| A Scripting Engine for Combining Design Transformations | 1 | 0.35 | 2010 |
| Customizable Composition and Parameterization of Hardware Design Transformations | 3 | 0.41 | 2010 |
| Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: a geometric programming framework | 34 | 1.66 | 2009 |
| Optimising designs by combining model-based and pattern-based transformations | 9 | 0.71 | 2009 |
| Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework | 1 | 0.37 | 2008 |
| Automatic On-chip Memory Minimization for Data Reuse | 15 | 0.85 | 2007 |
| Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm | 1 | 0.43 | 2006 |
