Name
Abstract | ||
|---|---|---|
A new programmable duty cycle corrector (PDCC) with variable duty cycle of output clock and synchronization of the input clock and output clock is proposed. Since the conventional pulse-width control circuits can adjust duty cycle but canpsilat synchronize the input and output clocks, the proposed PDCC uses a 2nd-order Delta-Sigma modulator to produce more several kinds of duty-cycle selection of clock signals with a 7-bit resolution. Simulated in a 0.18 um CMOS technology, the proposed PDCC can operate from 500 MHz to 800 MHz and the duty-cycle range of input clock can be operated from 10% to 90%. Moreover, the duty cycle of the output clock can be adjusted from 25% to 75% in a fine step of 0.78%. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746293 | APCCAS |
Keywords | Field | DocType |
cmos integrated circuits,input clock,programmable duty cycle corrector,variable duty cycle,delta-sigma modulated pwm mechanism,delta-sigma modulation,cmos technology,synchronization,output clock,pulse-width control circuits,pulse width modulation,synchronisation,delta sigma modulation,digital control,duty cycle,modulation,phase locked loops | Phase-locked loop,Synchronization,Computer science,Duty cycle,Control theory,Clock domain crossing,Pulse-width modulation,Pulse-frequency modulation,Electronic engineering,Input/output,Self-clocking signal | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 0 | 0.34 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gung-Yu Lin | 1 | 0 | 0.34 |
| Ching-Yuan Yang | 2 | 227 | 36.15 |
| Yu Lee | 3 | 11 | 3.21 |
| Jun-Hong Weng | 4 | 16 | 3.77 |