Name
Abstract | ||
|---|---|---|
Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL Convention Logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TVLSI.2007.903945 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
conventional atpg program,asynchronous null conventional logic,test point insertion,custom atpg library,asynchronous ncl design,asynchronous null convention logic,conventional automatic test pattern,test coverage,poor fault coverage,dft technique,ncl cyclic,fault coverage,design for testability,indexing terms,automatic test pattern generation,design for test,logic gates,logic design | Design for testing,Logic synthesis,Code coverage,Asynchronous communication,Automatic test pattern generation,Logic gate,Fault coverage,Computer science,Electronic engineering,Asynchronous circuit | Journal |
Volume | Issue | ISSN |
15 | 10 | 1063-8210 |
Citations | PageRank | References |
4 | 0.48 | 9 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Venkat Satagopan | 1 | 6 | 1.21 |
| Bonita Bhaskaran | 2 | 6 | 1.89 |
| Waleed K. Al-assadi | 3 | 17 | 5.31 |
| Scott C. Smith | 4 | 129 | 18.15 |
| Sindhu Kakarla | 5 | 7 | 1.89 |
| Al-Assadi, W.K. | 6 | 11 | 2.29 |