Name
Abstract | ||
|---|---|---|
We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1391469.1391523 | Anaheim, CA |
Keywords | Field | DocType |
average performance,delay sensor insertion,network synthesis,internal timing violations,sequential circuits,automated design,variable clock skew buffers,self-adjusting,delay monitoring,timing circuits,delay sensors,self-adjusting pipelines,variable clock skews,self-adjusting enhancement,self-adjusting pipeline structure,internal timing violation,delay circuits,chip performance,variable clock skew buffer,stochastic mixed-integer programming problem,delay sensor,pipeline stage,electronic design automation,simulated annealing,sensors,pipelines,clock skew,logic gates,robustness,process variation,manufacturing,hardware,chip,stochastic processes | Simulated annealing,Timing failure,Pipeline transport,Sequential logic,Computer science,Electronic engineering,Real-time computing,Chip,Robustness (computer science),Clock skew,Electronic design automation | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-60558-115-6 | 2 |
PageRank | References | Authors |
0.39 | 11 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jieyi Long | 1 | 129 | 8.98 |
| Seda Öǧrenci Memik | 2 | 488 | 42.57 |