Name
Abstract | ||
|---|---|---|
A 1024-bit RSA encryption LSI with DES and MD5 functions was developed. An RSA accelerator core implemented in the LSI is 4.9 MM2 in area, and has three 1024-bit adders that perform doubling, squaring, and exponential operations simultaneously. A 1024-bit RSA operation takes 23 msec with 100mA peak current at the maximum frequency of 45 MHz. A 1024-bit RSA key is generated in 0.3 sec by using arithmetic functions supported by the LSI. The throughputs of DES and MD5 at 45 MHz are 18.9 MB/sec and 29.7 MB/sec, respectively. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1007/BFb0030419 | ISW |
Keywords | Field | DocType |
low power dissipation,high-speed small rsa encryption,arithmetic function | Arithmetic function,Adder,Dissipation,Modular arithmetic,Computer science,Parallel computing,Smart card,Encryption,MD5,Computer hardware,Modular exponentiation | Conference |
Volume | ISSN | ISBN |
1396 | 0302-9743 | 3-540-64382-6 |
Citations | PageRank | References |
10 | 2.51 | 7 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akashi Satoh | 1 | 866 | 69.99 |
| Y. Kobayashi | 2 | 10 | 2.51 |
| H. Niijima | 3 | 16 | 3.20 |
| Nobuyuki Ooba | 4 | 13 | 3.05 |
| Seiji Munetoh | 5 | 327 | 33.14 |
| S. Sone | 6 | 10 | 2.51 |