| Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. | 5 | 0.54 | 2014 |
| Bitstream Protection In Dynamic Partial Reconfiguration Systems Using Authenticated Encryption | 4 | 0.42 | 2013 |
| A Fast Power Current Simulation Of Cryptographic Vlsi Circuits For Side Channel Attack Evaluation | 0 | 0.34 | 2013 |
| Evaluation Of Information Leakage From Cryptographic Hardware Via Common-Mode Current | 1 | 0.36 | 2012 |
| Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates | 21 | 1.63 | 2012 |
| A Configurable On-Chip Glitchy-Clock Generator For Fault Injection Experiments | 4 | 0.43 | 2012 |
| A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. | 4 | 0.50 | 2011 |
| Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function | 0 | 0.34 | 2011 |
| High-Performance Architecture For Concurrent Error Detection For Aes Processors | 0 | 0.34 | 2011 |
| An on-chip glitchy-clock generator for testing fault injection attacks. | 9 | 0.53 | 2011 |
| Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs | 52 | 2.72 | 2010 |
| Profiling Attack Using Multivariate Regression Analysis | 10 | 0.61 | 2010 |
| Prototyping platform for performance evaluation of SHA-3 candidates | 9 | 0.89 | 2010 |
| Comparative Power Analysis of Modular Exponentiation Algorithms | 14 | 0.67 | 2010 |
| A Design Methodology For A Dpa-Resistant Circuit With Rsl Techniques | 2 | 0.37 | 2010 |
| Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules | 5 | 0.56 | 2009 |
| A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques | 22 | 0.94 | 2009 |
| Evaluation Of Simple/Comparative Power Analysis Against An Rsa Asic Implementation | 0 | 0.34 | 2009 |
| Is the differential frequency-based attack effective against random delay insertion? | 3 | 0.50 | 2009 |
| Compact And High-Speed Hardware Architectures For Hash Function Tiger | 1 | 0.40 | 2009 |
| A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks | 7 | 0.72 | 2008 |
| High-Performance Concurrent Error Detection Scheme for AES Hardware | 39 | 1.37 | 2008 |
| Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs | 27 | 1.30 | 2008 |
| Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool | 1 | 0.35 | 2008 |
| Enhanced power analysis attack using chosen message against RSA hardware implementations | 8 | 0.63 | 2008 |
| Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems | 22 | 1.12 | 2008 |
| Systematic Design Of High-Radix Montgomery Multipliers For Rsa Processors | 3 | 0.54 | 2008 |
| Chosen-Message Spa Attacks Against Fpga-Based Rsa Hardware Implementations | 5 | 0.56 | 2008 |
| Enhanced Correlation Power Analysis Using Key Screening Technique | 5 | 0.44 | 2008 |
| High-performance ASIC implementations of the 128-bit block cipher CLEFIA | 7 | 0.77 | 2008 |
| High-Speed Parallel Hardware Architecture for Galois Counter Mode | 13 | 1.65 | 2007 |
| SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier | 0 | 0.34 | 2007 |
| High-resolution side-channel attack using phase-based waveform matching | 32 | 2.09 | 2006 |
| Hardware architecture and cost estimates for breaking SHA-1 | 1 | 0.37 | 2005 |
| A Scalable Dual-Field Elliptic Curve Cryptographic Processor | 133 | 7.68 | 2003 |
| Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI | 12 | 1.25 | 2002 |
| An Optimized S-Box Circuit Architecture for Low Power AES Design | 104 | 7.51 | 2002 |
| A Compact Rijndael Hardware Architecture with S-Box Optimization | 268 | 24.82 | 2001 |
| High-Speed MARS Hardware | 3 | 0.53 | 2000 |
| A High-Speed Small RSA Encryption LSI with Low Power Dissipation | 10 | 2.51 | 1997 |
