Name
Abstract | ||
|---|---|---|
This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1900008.1900020 | ACM Southeast Regional Conference 2005 |
Keywords | Field | DocType |
private l1-cache,high priority thread,time-predictable dual-core architecture,xilinx fpga,multi-core architecture,xilinx ise,various cache replacement algorithm,time-predictable dual-core prototype,virtex-6 fpga,5-stage in-order pipeline,l2 cache | Architecture,Computer architecture,CPU cache,Cache,Computer science,Field-programmable gate array,Cache algorithms,Thread (computing),Verilog,Adaptive replacement cache | Conference |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satya Mohan Raju Gudidevuni | 1 | 0 | 0.34 |
| Wei Zhang | 2 | 163 | 11.75 |