Paper Info
Title
An Analysis of the Double-Precision Floating-Point FFT on FPGAs
Abstract
Advances in FPGA technology have led to dramatic improvements in double precision floating-point performance. Modern FPGAs boast several GigaFLOPs of raw computing power. Unfortunately, this computing power is distributed across 30 floating-point units with over 10 cycles of latency each. The user must find two orders of magnitude more parallelism than is typically exploited in a single microprocessor; thus, it is not clear that the computational power of FPGAs can be exploited across a wide range of algorithms. This paper explores three implementation alternatives for the Fast Fourier Transform (FFT) on FPGAs. The algorithms are compared in terms of sustained performance and memory requirements for various FFT sizes and FPGA sizes. The results indicate that FPGAs are competitive with microprocessors in terms of performance and that the "correct" FFT implementation varies based on the size of the transform and the size of the FPGA.
Year
DOI
Venue
2005
10.1109/FCCM.2005.16
FCCM
Keywords
Field
DocType
double-precision floating-point fft,modern fpgas,fft,double precision floating-point performance,fast fourier transform,ieee floating point,fpga size,computing power,fpga technology,fft implementation,raw computing power,computational power,fpga,various fft size,sustained performance,reconfigurable computing,computer architecture,distributed computing,floating point unit,floating point,fast fourier transforms,field programmable gate arrays,parallel processing,matrix decomposition,concurrent computing,floating point arithmetic
Floating point,Computer science,Microprocessor,Parallel computing,Double-precision floating-point format,Field-programmable gate array,Fourier transform,Fast Fourier transform,IEEE floating point,Reconfigurable computing
Conference
ISBN
Citations 
PageRank 
0-7695-2445-1
25
1.89
References 
Authors
15
2
Name
Order
Citations
PageRank
K. Scott Hemmert157750.62
Keith D. Underwood284777.39