Name
Affiliation
Papers
KEITH D. UNDERWOOD
Univ Notre Dame, Dept Comp Sci & Engn, Notre Dame, IN 46545 USA
56
Collaborators
Citations 
PageRank 
89
847
77.39
Referers 
Referees 
References 
1662
1229
701
Search Limit
1001000
Title
Citations
PageRank
Year
Fast Networks and Slow Memories: A Mechanism for Mitigating Bandwidth Mismatches00.342017
Enabling Scalable High-Performance Systems with the Intel Omni-Path Architecture.60.592016
Remote Memory Access Programming in MPI-3150.722015
Exploiting Offload Enabled Network Interfaces30.372015
Intel® Omni-path Architecture: Enabling Scalable, High Performance Fabrics301.262015
Reducing Synchronization Overhead Through Bundled Communication60.682014
Evaluating on-die interconnects for a 4 TB/s router10.372013
Exploiting communication and packaging locality for cost-effective large scale networks40.422012
A low impact flow control implementation for offload communication interfaces20.422012
Enhanced Support for OpenSHMEM Communication in Portals80.712011
Using triggered operations to offload rendezvous messages60.472011
Scientific Application Demands on a Reconfigurable Functional Unit Interface30.392011
Enabling Flexible Collective Communication Offload with Triggered Operations100.662011
Challenges for High-Performance Networking for Exascale Computing30.472010
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs110.812010
Using triggered operations to offload collective communication operations80.572010
Performance evaluation of the Red Storm dual-core upgrade00.342010
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs201.062008
High Message Rate, Nic-Based Atomics: Design And Performance Considerations10.382008
Evaluating NIC hardware requirements to achieve high message rate PGAS support on multi-core processors80.602007
An architecture to perform NIC based MPI matching40.482007
Scientific Application Acceleration with Reconfigurable Functional Units110.972007
Floating-point divider design for FPGAs60.502007
SeaStar Interconnect: Balanced Bandwidth for Scalable Performance563.732006
Reconfigurable supercomputing - Is high-performance reconfigurable computing the next supercomputing paradigm?00.342006
Tools and techniques for performance - Architectures and APIs: assessing requirements for delivering FPGA performance to applications00.342006
Embedded floating-point units in FPGAs282.592006
Open Source High Performance Floating-Point Modules141.092006
Challenges and issues in benchmarking MPI20.452006
A preliminary analysis of the infinipath and XD1 network interfaces81.072006
Implications of application usage characteristics for collective communication offload180.912006
Poster reception - The structural simulation toolkit: exploring novel architectures20.362006
The implications of working set analysis on supercomputing memory hierarchy design121.432005
A Hardware Acceleration Unit for MPI Queue Processing201.012005
An Analysis of the Double-Precision Floating-Point FFT on FPGAs251.892005
Analyzing the Impact of Overlap, Offload, and Independent Progress for Message Passing Interface Applications271.622005
Enhancing NIC Performance for MPI using Processing-in-Memory50.502005
Initial Performance Evaluation of the Cray SeaStar Interconnect191.762005
Considering the Relative Importance of Network Performance and Network Features00.342005
RC-BLAST: Towards a Portable, Cost-Effective Open Source Hardware Implementation302.182005
The Impact of MPI Queue Usage on Message Latency272.092004
An Initial Analysis of the Impact of Overlap and Independent Progress for MPI111.132004
An Analysis of NIC Resource Usage for Offloading MPI261.962004
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance696.872004
FPGAs vs. CPUs: trends in peak floating-point performance12911.022004
An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster50.572004
An analysis of the impact of MPI overlap and independent progress282.392004
A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC30.492003
Analysis Of A Prototype Intelligent Network Interface40.532003
Evaluation of an Eager Protocol Optimization for MPI201.342003
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