Name
Abstract | ||
|---|---|---|
The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults Occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for ally input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transfun.E92.A.2295 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing | Digital electronics,Sequential logic,Pass transistor logic,Logic optimization,Theoretical computer science,Resistor–transistor logic,Logic level,Logic family,Mathematics,Asynchronous circuit | Journal |
Volume | Issue | ISSN |
E92A | 9 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuteru Namba | 1 | 114 | 27.93 |
| Hideo Ito | 2 | 100 | 17.45 |