Hideo Ito - Citegraph

Author Info

Name	Affiliation	Papers
HIDEO ITO	Chiba Univ, Grad Sch Adv Integrat Sci, Inage Ku, Chiba 2638522, Japan	36
Collaborators	Citations	PageRank
24	100	17.45
Referers	Referees	References
224	504	346

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100504

Publications (36 rows)

Collaborators (24 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Improving Small-Delay Fault Coverage Of On-Chip Delay Measurement By Segmented Scan And Test Point Insertion	0	0.34	2014
Scan Shift Time Reduction Using Test Compaction For On-Chip Delay Measurement	1	0.46	2014
Design For Delay Measurement Aimed At Detecting Small Delay Defects On Global Routing Resources In Fpga	0	0.34	2013
Improving Test Coverage By Measuring Path Delay Time Including Transmission Time Of Ff	0	0.34	2013
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop	0	0.34	2013
An on-chip delay measurement technique using signature registers for small-delay defect detection	6	0.53	2012
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits	1	0.35	2011
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture.	0	0.34	2011
Construction Of Bilbo Ff With Soft-Error-Tolerant Capability	0	0.34	2011
Quantitative Evaluation of Integrity for Remote System Using the Internet	0	0.34	2010
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit	8	0.60	2010
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing	9	0.87	2010
Single-Event-Upset Tolerant Rs Flip-Flop With Small Area	0	0.34	2010
Single Event Induced Double Node Upset Tolerant Latch.	5	0.97	2010
Soft Error Tolerant BILBO FF.	1	0.40	2010
Chiba Scan Delay Fault Testing with Short Test Application Time	1	0.36	2010
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding	0	0.34	2009
Testing of Switch Blocks in Three-Dimensional FPGA	1	0.39	2009
A Delay Measurement Technique Using Signature Registers	4	0.49	2009
Design For Delay Fault Testability Of Dual Circuits Using Master And Slave Scan Paths	0	0.34	2009
Test Compression For Robust Testable Path Delay Fault Testing Using Interleaving And Statistical Coding	1	0.37	2009
Design For Delay Fault Testability Of 2-Rail Logic Circuits	0	0.34	2009
Construction Of Soft-Error-Tolerant Ff With Wide Error Pulse Detecting Capability	0	0.34	2009
Analysis Of Path Delay Fault Testability For Two-Rail Logic Circuits	0	0.34	2009
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.	0	0.34	2008
Soft Error Hardened FF Capable of Detecting Wide Error Pulse	3	0.44	2008
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger	7	0.67	2008
Path Delay Fault Test Set for Two-Rail Logic Circuits	1	0.39	2008
Delay Fault Testability on Two-Rail Logic Circuits	2	0.44	2008
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing	0	0.34	2007
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit	30	2.32	2006
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices	4	0.63	2006
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters	2	0.42	2006
Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable	7	0.49	2006
Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift	3	0.40	2005
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core	3	0.40	2004