Name
Abstract | ||
|---|---|---|
Routing tools consume a significant portion of the total design time. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. In this paper we are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. The objective is to minimize this routability cost function . Our cost function is consistently able to indicate improved routability. Our method yields up to 50 % improvement over existing clustering methods in terms of the number of routing tracks required. The average improvement obtained is 16.5 %. Reduction in number of tracks yields reduced routing area. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/370155.370567 | ASP-DAC |
Keywords | Field | DocType |
average improvement,routability metrics,faster design process,routability-driven packing,routability-driven clustering method,clustering method,cluster-based fpgas,total design time,method yield,cost function,routability cost function,improved routability,intellectual property,logic circuits,system on a chip,computer science,field programmable gate arrays,design process,routing,cores,network routing,circuit complexity,design automation | Cluster (physics),Logic gate,System on a chip,Circuit complexity,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Electronic engineering,Electronic design automation,Cluster analysis,Design process | Conference |
ISBN | Citations | PageRank |
0-7803-6634-4 | 24 | 1.45 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Elaheh Bozorgzadeh | 1 | 630 | 37.93 |
| Seda Ogrenci-Memik | 2 | 148 | 7.68 |
| Majid Sarrafzadeh | 3 | 3103 | 317.63 |