Name
Abstract | ||
|---|---|---|
Non-volatile flash memories are becoming more and more popular for system-on-chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15mum NOR-based embedded flash structure |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VTS.2006.19 | Berkeley, CA |
Keywords | Field | DocType |
large block,profile fault simulation performance,path delay fault simulation,flash memories,functional test vector suite,multi-cycle delay path,industrial design,failure mechanisms,embedded systems,test methods,logic gates,system on chip,fault model | Logic gate,System on a chip,Computer science,Transistor circuits,Electronic engineering,Transistor,Embedded system | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2514-8 | 9 |
PageRank | References | Authors |
1.07 | 5 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| O. Ginez | 1 | 25 | 4.28 |
| J. -M. Daga | 2 | 36 | 11.05 |
| M. Combe | 3 | 9 | 1.07 |
| P. Girard | 4 | 69 | 6.89 |
| C. Landrault | 5 | 178 | 13.49 |
| S. Pravossoudovitch | 6 | 689 | 54.12 |
| A. Virazel | 7 | 169 | 23.25 |