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C. LANDRAULT
Author Info
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Name
Affiliation
Papers
C. LANDRAULT
Université de Montpellier II / CNRS, France
13
Collaborators
Citations
PageRank
18
178
13.49
Referers
Referees
References
385
266
156
Search Limit
100
385
Publications (13 rows)
Collaborators (18 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash
2
0.44
2009
Yield Improvement, Fault-Tolerance to the Rescue?
4
0.90
2008
Using TMR Architectures for Yield Improvement
20
1.65
2008
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories
2
1.05
2007
DERRIC: A Tool for Unified Logic Diagnosis
13
0.72
2007
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs
3
0.44
2007
Slow write driver faults in 65nm SRAM technology: analysis and March test solution
6
0.55
2007
An Overview of Failure Mechanisms in Embedded Flash Memories
9
1.07
2006
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
10
0.74
2001
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
71
3.12
2001
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
26
1.66
2000
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
1
0.35
1999
A Ring Architecture Strategy for BIST Test Pattern Generation
11
0.81
1998
1