Name
Abstract | ||
|---|---|---|
For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit path delay fault grading on with a GPGPU implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50x speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200x speedup is observed against a single-threaded, more complex version in the framework which grades more faults. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2591513.2591539 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
fault simulation,testing,and fault-tolerance,gpgpu,path delay fault grading,reliability | Automatic test pattern generation,Subroutine,Fault coverage,Computer science,Parallel computing,Real-time computing,Static timing analysis,General-purpose computing on graphics processing units,Xeon,Fault grading,Speedup | Conference |
ISSN | Citations | PageRank |
1066-1395 | 1 | 0.36 |
References | Authors | |
18 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joseph Lenox | 1 | 1 | 0.70 |
| Spyros Tragoudas | 2 | 625 | 88.87 |