Name
Abstract | ||
|---|---|---|
Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/DELTA.2002.994670 | DELTA |
Keywords | Field | DocType |
relevant criterion,big concern,recent approach,test power,interesting direction,large soc designs,embedded core,new low power testing,big issue,integrated circuit,large system-on-chip design,low power electronics,system testing,satisfiability,power dissipation,system on a chip,system on chip | System on a chip,System testing,Dissipation,Computer science,Automatic testing,Electronic engineering,Embedded core,Electrical engineering,Integrated circuit,Test power,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-1453-7 | 15 | 0.81 |
References | Authors | |
24 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Bonhomme | 1 | 186 | 12.16 |
| P. Girard | 2 | 478 | 41.91 |
| Christian Landrault | 3 | 200 | 19.16 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |