Name
Abstract | ||
|---|---|---|
In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It isproved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly unreachable states. Experimental results for ISCAS benchmark circuits are shown. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ATS.2001.990253 | Asian Test Symposium |
Keywords | Field | DocType |
test generation method,sequential circuit,multiple unreachable states,iscas benchmark circuit,incoming transition,test generation,undetectable fault,sequential redundancy removal,unreachable state,logic gates,benchmark testing,combinational circuits,redundancy,sequential analysis,signal processing,sequential circuits | Signal processing,Logic gate,Sequential logic,Computer science,Automatic testing,Combinational logic,Real-time computing,Electronic engineering,Redundancy (engineering),Electronic circuit,Benchmark (computing) | Conference |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Shinsuke Hata | 2 | 0 | 0.34 |
| Masaki Hashizume | 3 | 98 | 27.83 |
| Takeomi Tamesada | 4 | 45 | 12.49 |