Title
A 45-Nm 37.3 Gops/W Heterogeneous Multi-Core Soc With 16/32 Bit Instruction-Set General-Purpose Core
Abstract
We built a 12.4 mm x 12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.
Year
DOI
Venue
2011
10.1587/transele.E94.C.663
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
heterogeneous, instruction set, MMU
32-bit,Instructions per cycle,Single-core,System on a chip,Physical address,Instruction set,Computer science,16-bit,Computer hardware,Multi-core processor,Embedded system
Journal
Volume
Issue
ISSN
E94C
4
1745-1353
Citations 
PageRank 
References 
0
0.34
3
Authors
12
Name
Order
Citations
PageRank
Osamu Nishii15914.00
Yoichi Yuyama2173.06
Masayuki Ito300.34
Yoshikazu Kiyoshige4222.31
Yusuke Nitta5295.72
Makoto Ishikawa6234.26
Tetsuya Yamada7213.48
Junichi Miyakoshi87817.73
Yasutaka Wada97211.19
Keiji Kimura1012023.20
Hironori Kasahara1128544.35
Hideo Maejima12294.74