Paper Info
Title
Shield count minimization in congested regions
Abstract
With worsening crosstalk in nanometer designs, it is becoming increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by adding shields adjacent to these wires. However, the number of wires requiring shields in high frequency designs becomes extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels in this paper, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer. Our approach has proven highly effective while designing some high frequency blocks of a commercial gigahertz range microprocessor.
Year
DOI
Venue
2002
10.1145/505388.505409
ISPD
Keywords
Field
DocType
critical signal net,domino circuits,power grid,high frequency design,routing,shielding,crosstalk,noise,congested region,adaptive power,fewest new power line,shield count minimization,high frequency block,large area impact,fine-grained power grid,layout,high performance design,power routing,critical wire,high frequency,satisfiability
Multipath routing,Mathematical optimization,Computer science,Electromagnetic shielding,Microprocessor,Electric power transmission,Minification,Routing (electronic design automation),Shields,Electrical engineering,Shield
Conference
ISBN
Citations 
PageRank 
1-58113-460-6
4
0.59
References 
Authors
11
2
Name
Order
Citations
PageRank
Prashant Saxena121025.24
s p gupta271.04