Name
Abstract | ||
|---|---|---|
In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/VTEST.1996.510880 | VTS |
Keywords | Field | DocType |
efficient solution,high speed pseudo,cmos tspc cell,hspice simulation,random testing,testable functionally equivalent logic,high speed cmos circuit,tspc circuit,untestable fault,test methodology,built-in self-test scheme,integrated circuit layout | Integrated circuit layout,Test method,Spice,Computer science,Electronic engineering,CMOS,Logic block,Electronic circuit,Pseudo random testing,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-8186-7304-4 | 1 | 0.43 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Soufi | 1 | 1 | 0.43 |
| S. Rochon | 2 | 1 | 0.43 |
| Y. Savaria | 3 | 119 | 26.71 |
| Bozena Kaminska | 4 | 1155 | 189.76 |