Y. Savaria - Citegraph

Author Info

Name	Affiliation	Papers
Y. SAVARIA	ECOLE POLYTECH,DEPT ELECT & COMP ENGN,MONTREAL H3C 3A7,QUEBEC,CANADA	34
Collaborators	Citations	PageRank
82	119	26.71
Referers	Referees	References
267	379	177

Search Limit

100379

Publications (34 rows)

Collaborators (82 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning	0	0.34	2021
RISC-V Barrel Processor for Deep Neural Network Acceleration	0	0.34	2021
Analog Circuits to Accelerate the Relaxation Process in the Equilibrium Propagation Algorithm	0	0.34	2020
OTA-Free MASH 2-2 Noise Shaping SAR ADC - System and Design Considerations.	0	0.34	2020
Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers	0	0.34	2020
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits	0	0.34	2019
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.	1	0.36	2018
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design	7	0.77	2013
A very-high output impedance charge pump for low-voltage low-power PLLs	4	0.44	2009
A high-level requirements engineering methodology for electronic system-level design	0	0.34	2007
Soft-error classification and impact analysis on real-time operating systems	11	0.81	2006
A Metric for Automatic Word-Length Determination of Hardware Datapaths	2	0.41	2006
Evaluation of a software-based error detection technique by RT-level fault injection	0	0.34	2006
A system level implementation strategy and partitioning heuristic for LUT-based applications	0	0.34	2005
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique	1	0.36	2004
SIED: software implemented error detection	9	0.64	2003
Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders	1	0.35	2003
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs	22	4.26	2002
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI	7	1.23	1999
Design of Clock Distribution Networks in Presence of Process Variations	6	0.97	1998
A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing	0	0.34	1998
Design and performance of CMOS TSPC cells for high speed pseudo random testing	1	0.43	1996
Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems.	3	0.60	1996
Timing analysis speed-up using a hierarchical and a multimode approach	2	0.41	1996
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors	5	1.08	1995
On the design of at-speed testable VLSI circuits	0	0.34	1995
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits	1	0.37	1995
A new method for testing mixed analog and digital circuits	1	0.36	1995
Cost analysis of a new algorithmic-based soft-error tolerant architecture.	0	0.34	1995
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits	2	0.45	1994
A pragmatic approach to the design of self-testing circuits	8	0.79	1989
New architectures for fast convolutional encoders and threshold decoders	6	1.03	1988
Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits	17	3.76	1986
A design for machines with built-in tolerance to soft errors	2	2.76	1984