Name
Title | ||
|---|---|---|
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty |
Abstract | ||
|---|---|---|
Leakage power currently comprises a large fraction of the total power consumption of an IC. Techniques to minimize leakage have been researched widely. However, most approaches to reducing leakage have an associated performance penalty. In this article, we present an approach which minimizes leakage by simultaneously modifying the circuit while deriving the input vector that minimizes leakage. In our approach, we selectively modify a gate so that its output (in sleep mode) is in a state which helps minimize the leakage of other gates in its transitive fanout. Gate replacement is performed in a slack-aware manner, to minimize the resulting delay penalty. One of the major advantages of our technique is that we achieve a significant reduction in leakage without increasing the delay of the circuit. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1870109.1870118 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
associated performance penalty,low power,significant reduction,leakage,gate replacement,minimizes leakage,circuit modification technique,zero delay penalty,total power consumption,large fraction,leakage power,reduce leakage,subthreshold leakage,input vector control,resulting delay penalty,simultaneous input vector control,asic,input vector,major advantage | Leakage (electronics),Control theory,Computer science,Leakage power,Real-time computing,Application-specific integrated circuit,Input vector control,Subthreshold conduction,Sleep mode,Power consumption | Journal |
Volume | Issue | ISSN |
16 | 1 | 1084-4309 |
Citations | PageRank | References |
3 | 0.42 | 16 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nikhil Jayakumar | 1 | 215 | 20.42 |
| Sunil P. Khatri | 2 | 1213 | 137.09 |