Nikhil Jayakumar - Citegraph

Author Info

Name	Affiliation	Papers
NIKHIL JAYAKUMAR	Texas A&M University, College Station, TX	27
Collaborators	Citations	PageRank
35	215	20.42
Referers	Referees	References
464	395	243

Search Limit

100464

Publications (27 rows)

Collaborators (35 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A low-jitter phase-locked resonant clock generation and distribution scheme	0	0.34	2013
ISPD 2013 expert designer/user session (eds)	0	0.34	2013
An Automated Approach for Minimum Jitter Buffered H-Tree Construction	1	0.40	2011
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty	3	0.42	2010
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations	26	1.22	2009
Circuit-level design approaches for radiation-hard digital electronics	9	1.51	2009
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations	7	0.56	2008
A Predictably Low-Leakage ASIC Design Style	3	0.55	2007
A Structured Asic Design Approach Using Pass Transistor Logic	8	0.50	2007
An algorithm to minimize leakage through simultaneous input vector control and circuit modification	6	0.50	2007
A design flow to optimize circuit delay by using standard cells and PLAs	3	0.54	2006
Network coding for routability improvement in VLSI	6	0.47	2006
A probabilistic method to determine the minimum leakage vector for combinational designs	3	0.41	2006
A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes	2	0.44	2006
On the Improvement of Statistical Static Timing Analysis	0	0.34	2006
A design approach for radiation-hard digital electronics	33	2.33	2006
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs	1	0.35	2005
Minimum Energy Near-threshold Network of PLA based Design	4	1.19	2005
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents	5	0.52	2005
Non-Manhattan Routing Using a Manhattan Router	3	0.44	2005
A variation tolerant subthreshold design approach	12	1.75	2005
X-Routing using Two Manhattan Route Instances	0	0.34	2005
A metal and via maskset programmable VLSI design methodology using PLAs	23	1.57	2004
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems	3	0.47	2004
A novel clock distribution and dynamic de-skewing methodology	27	1.42	2004
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells	5	0.49	2003
Dos and don'ts of CTL state coverage estimation	22	1.00	2003