Paper Info
Title
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
Abstract
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of outmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm of [3] by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of data flow graphs and investigated the impact on circuit area when applying different power constraints.
Year
DOI
Venue
2003
10.1109/DATE.2003.1253770
DATE
Keywords
Field
DocType
increased battery lifetime,power awareness,power constrained high-level synthesis,large power spike,different power constraint,battery powered digital systems,partial-clique partitioning algorithm,high-level synthesis algorithm,circuit area,heuristic algorithm,maximum power,power feasible schedule,binding problem,management,design,hierarchical,algorithms,area,network flow,floorplanning,embedded system,simulated annealing,allocation,high level synthesis,algorithm design and analysis,latency,data flow graph,scheduling,scheduling algorithm
Flow network,Simulated annealing,Algorithm design,Computer science,Heuristic (computer science),Parallel computing,High-level synthesis,Real-time computing,Schedule,Maximum power principle,Battery (electricity)
Conference
ISBN
Citations 
PageRank 
0-7695-1870-2
0
0.34
References 
Authors
6
2
Name
Order
Citations
PageRank
S. F. Nielsen161.34
Jan Madsen257656.90